As shown in FIG. 1, which is an illustrative view for showing a delta-sigma digital-to-analog converter. The delta-sigma digital-to-analog converter comprises an interpolation filter 1, a noise shaping loop 2, a digital-to-analog converter 3 and an analog low-pass filter 4, wherein a digital signal D is inputted to the interpolation filter 1, and an analog signal A is outputted from the analog low-pass filter 4.
FIG. 2(a) shows a circuit diagram of the digital-to-analog converter 3, located at the left side of which is the circuit for generating reference voltage, including resistors R1, R2, R3 and operational amplifiers 21, 22 which are electrically connected as shown. The generated reference voltage Vref+ and Vref− will be inputted respectively to an end of the switches 24, 25, 26 and 28. Located at the right side of FIG. 2(a) is an digital-to-analog converter comprising switches 23, 24, 25, 26, 28, 29, a sampling capacitor Cs, an integrating capacitor Ci and an integrating operational amplifier 27, which are connected as shown.
FIG. 2(b) is an illustrative view of the signals for controlling the switches 23, 24, 25, 26, 28 and 29, wherein φ1 controls the switches 24, 25, 26 and 28, and φ2 controls the switches 23 and 29. The high level means that the switch is closed, while the lower level represents opening of the switch. The φ1, the input signal IN (output of the noise shaping loop 2) are inputted to AND gate 1 (AND 1), the inverter (INV), and AND gate (AND2), the connection is shown in FIG. 2(a). When the signal φ1 is at high level, and the input signal IN is at high level, the switches 24, 26 are turned on, at this moment, the voltage difference (Vref+−Vref−) will charge the capacitor Cs. When the signal φ1 is at high level, and the input signal IN is at low level, the switches 25, 28 are turned on, the voltage difference (Vref−−Vref+) will charge the capacitor Cs. When the signal φ2 is at high level, the switches 23, 29 are turned on, at this moment the signal φ1 enables the switches 24, 25, 26 and 28 to be turned off, so that the charge on the sampling capacitor Cs and that on the integrating capacitor Ci will be averaged based on their respective capacitances, thus forming 1-bit digital-to-analog converting. If a plurality of sampling capacitors Cs1, Cs2, Cs3 . . . are parallel connected with Cs, and the sampling capacitors Cs1, Cs2, Cs3 . . . are provided with a plurality of switches, just like the switches 23, 24, 25, 26, 28, 29, then the charges on the sampling capacitors Cs, Cs1, Cs2, Cs3 . . . and the integrating capacitor Ci can be averaged simultaneously. Therefore, a so-called multi-bits digital-to-analog converter is formed.
However, as shown in FIG. 2, to make the reference voltages Vref+, Vref− of the digital-to-analog converter 3 more accurate, it must use the operational amplifiers 21, 22 as buffers, but the problem is that the operational amplifiers 21, 22 are big, it will increase the cost. Furthermore, when the capacitance of the sampling capacitors Cs, Cs1, Cs2, Cs3 . . . increases, the operational amplifiers 21, 22 will inevitably be increased in power consumption, this will lead to a further size increasing of the operational amplifiers 21, 22, and the cost will be increased much more.
The present invention has arisen to mitigate and/or obviate the afore-described disadvantages.